View HM67S36130SERIES_406137.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HM67S36130 Series
131,072-words x 36-bits Synchronous Fast Static RAM
ADE-203-659A(Z) Product Preview Rev. 1 Feb. 21, 1997 Features
* * * * * * * * * * 3.3V 5% Operation LVCMOS Compatible Input and Output Synchronous Operation Internal self-timed Late Write Asynchronous G Output Control Byte Write Control (4 byte write selects, one for each 9 bits) Power down mode is provided Differential PECL Clock Inputs Boundary Scan Protocol Single Clock Register-Latch Mode
Ordering Information
Type Number HM67S36130BP-7 Cycle Time 7.0 ns Package 119 Bump 1. 27 mm 14 mm x 22 mm BGA (BP-119)
All power supply and ground pins must be connected for proper operation of the device. This document contains information on a new product. Specifications and information contained herein are subject to change without notice.
HM67S36130 Series
Pin Arrangement
1 A
VDDQ SA16 SA13 NC SA10 SA7 VDDQ
2
3
4
5
6
7
B
NC NC SA12 NC SA11 NC NC NC
C
NC SA15 SA14 VDD SA9 SA8
D
DQc1 DQc0 VSS NC SS G VSS DQb8 DQb7 VSS DQb6 DQb5 VSS DQb4 VDDQ
E
DQc3 DQc2 VSS
F
VDDQ DQc4 VSS
G
DQc6 DQc5 SWEc NC SWEb DQb3 DQb2
H
DQc8 DQc7 VSS NC VDD K VSS DQb1 DQb0 NC VDD VDDQ
J
VDDQ VDD NC
K
DQd0 DQd1 VSS VSS DQa7 DQa8 SWEa DQa5 DQa6
L
DQd2 DQd3 SWEd K
M
VDDQ DQd4 VSS SWE VSS DQa4 VDDQ
N
DQd5 DQd6 VSS SA2 VSS DQa2 DQa3
P
DQd7 DQd8 VSS SA3 VSS DQa0 DQa1
R
NC SA1 NC M1 VDD M2 SA5 NC NC ZZ
T
NC SA0 SA4 SA6
U
VDDQ TMS TDI TCK TDO NC VDDQ
(Top view)
2
HM67S36130 Series
Block Diagram
Comparator
SA0SA16
JTAG Register
Address Register1
Address Register2
(L) (H)
Multiplex 17 Decoder Memory Array (131072words x36bits) 36 Sense Amp. 36
SS JTAG Register SWE JTAG Register SWE a,b,c,d
Chip Enable Register Global Write Register Byte 4 Write Register1 4
9x4 Byte Write Driver 9x4
JTAG Register
Byte Write Register2
JTAG Register G JTAG Register DQa0-8 DQb0-8 DQc0-8 DQd0-8 ZZ JTAG Register JTAG Register K,K JTAG Register M1,M2 TDi TCK TMS TDO SAMPLE-Z JTAG Tap Controller I/O Bus Protocol Contorol Logic
Output Contorol Register (L) 36 Input Data Register 36 36 (H) Multiplex 36
4
Output 36 Data Register
Note:
The functional block diagram illustrates simplified device operation. See truth table, pin descriptions and timing diagrams for detailed information.
3
HM67S36130 Series
Pin Descriptions
Name VDD VSS VDDQ K K SS SWE SAn SWEx G ZZ DQxm M1, M2 TMS TCK TDI TDO NC Input Input Input Input Input Input Input Input I/O Input Input Input Input Output I/O Type Descriptions Power Supply Ground Output Power Supply Input Clock Input Clock Synchronous Chip Select Synchronous Write Enable Synchronous Address Synchronous Byte Select Asynchronous Output Enables Power Down Mode Select Synchronous Data Input/Output Output Protocol Mode Select Boundary Scan Test Mode Select Boundary Scan Test Clock Boundary Scan Test Data In Boundary Scan Test Data Out No Connection x = a, b, c, d m = 0, 1, 2, ... 8 1 n = 0, 1, 2, ... 16 x = a, b, c, d Note
Notes: 1. There is 1 protocol with using mode pins. Mode control pins (M1, M2) are to be tied to either V DD or V SS . The state of the Mode control inputs must be set before power-up and must not change during device operation. Mode control inputs are not standard inputs and may not meet VIH or VIL specifications.
M1 VDD
M2 VSS
Protocol Single Clock Register Latch
4
HM67S36130 Series
Truth Table
SS H L G X H SWE X H SWEa X X SWEb X X SWEc X X SWEd X X K L-H L-H K H-L H-L Operation Dead (not selected) Dead (Dummy read) Read Write a, b, c, d byte Write b, c, d byte Write a, c, d byte Write a, b, d byte Write a, b, c byte Write c, d byte Write a, d byte Write a, b byte Write b, c byte Write d byte Write c byte Write b byte Write a byte DQa High -Z High -Z Dout Din High -Z Din Din Din High -Z Din Din High -Z High -Z High -Z High -Z Din DQb High -Z High -Z Dout Din Din High -Z Din Din High -Z High -Z Din Din High -Z High -Z Din High -Z DQc High -Z High -Z Dout Din Din Din High -Z Din Din High -Z High -Z Din High -Z Din High -Z High -Z DQd High -Z High -Z Dout Din Din Din Din High -Z Din Din High -Z High -Z Din High -Z High -Z High -Z
L L L L L L L L L L L L L L
L X X X X X X X X X X X X X
H L L L L L L L L L L L L L
X L H L L L H L L H H H H L
X L L H L L H H L L H H L H
X L L L H L L H H L H L H H
X L L L L H L L H H L H H H
L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H
H-L H-L H-L H-L H-L H-L H-L H-L H-L H-L H-L H-L H-L H-L
Notes: 1. X means don't care for synchronous inputs, and H or L for asynchronous inputs. 2. SWE, SS, SWEa to SWEd, SA are sampled at the rising edge of K clock.
5
HM67S36130 Series
Absolute Maximum Ratings
Parameter Supply voltage Output Supply Voltage Voltage on any pin Operating Temperature Storage Temperature Input Latchup Current Output Current per pin Symbol VDD VDDQ VIN Ta Tstg (bias) I LI Iout Value -0.5 to +4.6 -0.5 to VDD+0.5 -0.5 to VDD+0.5 0 to 70 (Tj max = 110) -55 to 125 200 25 Unit V V V C C mA mA Note 1 1, 4 1, 4
Notes: 1. All voltage are referenced to VSS . 2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted the Operation Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 3. These Bi-CMOS memory circuits have been designed to meet the DC and AC specifications shown in the tables after thermal equilibrium has been established. 4. Not exceed 4.6 V 5. Power Up Initialization The following supply voltage application sequence is recommended: V SS , VDD then VDDQ. Remember according to the Absolute Maximum Ratings table, VDDQ is not to exceed VDD + 0.5 V, whatever the instantaneous value of V DD.
Recommended DC Operating Conditions (Ta = 0 to 70C [Tj max = 110C])
Parameter Supply voltage Output Supply voltage Symbol VDD VDDQ Min 3.135 3.135 2.375 Input voltage Logic High Level Logic Low Level Logic High Level Logic Low Level PECL Logic High Level PECL Logic Low Level Notes: 1. For VDDQ = 3.3 V supply. 2. For VDDQ = 2.5 V supply. VIH VIL VIH VIL VIH(PECL) VIL(PECL) 2.0 -0.5 1.85 -0.5 2.135 1.490 Typ 3.3 3.3 2.5 -- -- -- -- -- -- Max 3.465 3.465 2.75 VDDQ + 0.3 0.8 VDDQ + 0.3 1.15 2.420 1.825 Unit V V V V V V V V V 1 2 1 1 2 2 Notes
6
HM67S36130 Series
DC Characteristics (Ta = 0 to 70C,[Tjmax-110C], VDD = 3.3 V 5%)
Parameter Input Leakage Current Output Leakage Current PECL Input Leakage Current Low PECL Input Leakage Current High Symbol I LI I LO I LI (PECL) I LI (PECL) -- -- -- 0 2.4 VDDQ-0.4 Min -1 -1 Typ -- -- -- -- -- -- -- -- -- Max 1 1 50 150 600 2.7 100 0.4 VDDQ VDDQ Unit A A A A mA W mA V V V 3 3, 8 5 4 4, 6 4, 7 Note 1 2
VDD Operating Current excluding output I DD drivers Power Dissipation including output drivers Standby Current (Power down mode) Output Voltage Logic Low Logic High Note: 1. 2. 3. 4. 5. 6. 7. 8. Pd I SB VOL VOH
0 Vin V DD 0 VI/O V DD, Tristate I/O I(I/O) = 0 mA, Address increment read 50% / write 50%, VDD = VDD max, Frequency = 125 MHz I OH = -2 mA or IOL = 2 mA All inputs (except clock) are held at either VSS or VDDQ, and ZZ is held at V DDQ for VDDQ = 3.3 V supply for VDDQ = 2.5 V supply Output Load Capacitance = 29 pF
Input Capacitance (Ta = 25C, f = 1 MHz)
Parameter Address Input Capacitance Clock Input Capacitance I/O Capacitance Note: Symbol CINA CINC CINIO Min -- -- -- Max 5 8 7 Unit pF pF pF Pin Name SAn, SS, SWE, SWEx K, K, G DQxm Note 1 1 1
1. This value is measured by sampling and not 100% tested.
7
HM67S36130 Series
AC Test Conditions
* * * * * * * Temperature Input Reference Point for Differential Signals Input pulse levels Clock Input pulse levels Input Rise/Fall Time Clock input Rise/Fall Time Output timing reference (vih/vil) 0C Ta 70C (Tj max = 110C) Differential Cross-Over Point 0 to 2.5 V 1.8 to 2.1 V 0.5 to 1.5 ns (10% to 90%) 0.3 to 1.0 ns (10% to 90%) 2.0 V/0.8 V for VDDQ = 3.3 V 1.65 V/1.15 V for VDDQ = 2.5 V See figures Note
1 1
* Output load
Note: 1. These levels are efficent under open termination. load condition. These vih/vil levels under termination load will be determined by correlation between open load and termination load.
I/O
50
20pF (Including scope and jig capacitance)
1.4V
AC Timing Measurement
Vih Vil setup min Vih Vil max max hold setup min hold
8
HM67S36130 Series
AC Characteristics (0C Ta 70C [Tj max = 110C], V DD= 3.3V 5%)
Single Differential Clock Register-Latch Mode (M1 = VDD, M2 = VSS )
-7 Parameter Clock Control Clock Cycle Clock High Width Clock Low Width Read Control K Clock Access K Clock Access Output Enable Access K Low to Q Change Output Buffer Control K Low to Low-Z Output Enable to Low-Z K Clock High to Hi-Z Output Enable to Hi-Z Setup Times Address Setup Time Data Setup Time Hold Times Address Hold Time Data Hold Time t KHAX t KHDX 1.0 1.0 -- -- ns ns SA, SS, SWE, SWEa - SWEd t AVKH t DVKH 0.5 0.5 -- -- ns ns SA, SS, SWE, SWEa - SWEd t KLQX2 t GLQX t KHQZ t GHQZ 1.0 1.0 1.0 0.0 -- -- 3.0 3.5 ns ns ns ns 1 1 2 2 t KHQV t KLQV t GLQV t KLQX -- -- -- 1.0 7.0 3.0 3.5 -- ns ns ns ns t KHKH t KHKL t KLKH 8.0 2.0 2.0 -- -- -- ns ns ns Symbol Min Max Unit Notes
Notes: 1. Transition is measured 200 mV from steady voltage with specified loading in Test Load. 2. Transition is measured start point of output high impedance from output Low impedance.
9
HM67S36130 Series
Read Cycle 1
tKHKH K K SA A1 tAVKH SS tAVKH SWE tKHAX tKHKL tKLKH
tAVKH A2
tKHAX A3 tKHAX A4
SWEx tKHQV DQ Do 0 Do 1 tKLQV tKLQX Do 2 Do 3
Notes:
G = VIL
10
HM67S36130 Series
Read Cycle 2 (SS Controlled)
tKHKH K K SA A1 tAVKH SS tAVKH SWE tKHAX tKHAX tKHKL tKLKH
tAVKH A3
tKHAX A4
SWEx tKHQZ(Max) DQ Do 0 Do 1 tKHQZ(Min) Do 3 tKLQX2
Note:
1. 2.
G = VIL Do1 represents the output data for the input address A1.
11
HM67S36130 Series
Read Cycle 3 (G Controlled)
tKHKH K K SA A1 tAVKH SS tAVKH SWE tKHAX tKHKL tKLKH
tAVKH A2
tKHAX A3 tKHAX A4
SWEa-d
G tGHQZ(Max) DQ Do 0 Do 1 Do 2 tGHQZ(Min) tGLQX tGLQV Do 3
12
HM67S36130 Series
Write Cycle
tKHKH K K SA A1 tAVKH SS tAVKH SWE tAVKH SWEa-d G tDVKH DQ Di 0 Di 1 tKHDX Di 2 Di 3 tKHAX tKHAX tKHKL tKLKH
tAVKH A2
tKHAX A3 tKHAX A4
13
HM67S36130 Series
Read-Write Cycle
READ tKHKH K K SA SS tAVKH SWE tAVKH SWEa-d G(Low-Fix) tKHQV DQ Do 0 tKLQV tKLQX tKHQZ(max) Do 1 Do 2 tDVKH Di 3 tKHDX Do 4 tKLQV(max) Do 5 Di 6 tKHAX tKHAX A1 tAVKH A2 tKHAX A3 READ WRITE tKHKL tKLKH READ READ WRITE
tAVKH A4
tKHAX A5 A6 A7
(1) During this period DQ pins are in the output state so that the input signal of opposite phase to the outputs must not be applied.
14
HM67S36130 Series
Boundary Scan Test Access Port Operations
overview In order to perform the interconnect testing of the modules that include this SRAM, the serial boundary access port (TAP) is designed to operate in a manner consistent with IEEE Standard 1149.1 - 1990. But does not implement all of the functions required for 1149.1. the HM67S36130 contains a TAP contoroller. Instruction register, Boundary scan register, Bypass and ID register.
Test Access Port Pins
Symbol I/O TCK TMS TDI TDO Name Test Clock Test Mode Select Test Data In Test Data Out
Notes: This Device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. To disable the TAP, TCK must be connected to V SS . TDO should be left unconnected.
TAP DC Operating Characteristics (Ta = 0C to 70C [Tj max = 110C])
Parameter Boundary scan Input High voltage Boundary scan Input Low voltage Boundary scan Input Leakage Current Boundary scan Output Low voltage Boundary scan Output High voltage Notes: 1. 0 Vin V DD 2. I OL = 2 mA 3. I OH = -2 mA Symbol VIH VIL I LI VOL VOH 2.4 V Min 2.0 V -0.5 V -1A Max VDD + 0.3 V 0.8 V +1A 0.4 V 1 2 3 Note
15
HM67S36130 Series
TAP AC Operating Characteristics (Ta = 0C to 70C [Tj max = 110 C])
Parameter Test Clock Cycle Time Test Clock High Pulse Width Test Clock Low Pulse Width Test Mode Select Setup Test Mode Select Hold Capture Setup Capture Hold TDI Valid to TCK High TCK High to TDI Don't Care TCK Low to TDO Unknown TCK Low to TDO Valid Symbol t THTH t THTL t TLTH t MVTH t THMX t CS t CH t DVTH t THDX t TLQX t TLQV Min 67 30 30 10 10 10 10 10 10 0 -- Max -- -- -- -- -- -- -- -- -- -- 20 Unit ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. t CS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture.
16
HM67S36130 Series
TAP AC Test Conditions * * * * * * * Temperature Input Reference Point for Single-Ended Signals Input pulse levels Input Rise/Fall Time Output timing reference Test load termination supply voltage (VT ) Output Load 0C Ta 70C [Tj max = 110C] 1.5 V 0 to 2.5 V 2.0 ns typical (10% to 90%) 1.5 V 1.5 V See figures
VT DUT Z0 = 50 TDO 50
boundary scan AC test Load
17
HM67S36130 Series
TAP Timing Diagram
tTHTH TCK tTHTL tTLTH
tMVTH TMS
tTHMX
tDVTH TDI
tTHDX tTLQV tTLQX
TDO tCS RAM ADDRESS tCH
TAP Timing Diagram
18
HM67S36130 Series
Test Access Port Registers
Register Name Instruction Register Bypass Register ID Register Boundary Scan Register Length 3 bits 1 bits 32 bits 70 bits Symbol IR [0;2] BP ID [0;31] BS [1;70] Note
TAP Controller Instruction Set
IR2 0 0 0 0 1 1 1 1 IR1 0 0 1 1 0 0 1 1 IR0 0 1 0 1 0 1 0 1 Instruction SAMPLE-Z IDCODE SAMPLE-Z BYPASS SAMPLE BYPASS BYPASS BYPASS Tristate all data drivers and capture the pad value Operation Tristate all data drivers and capture the pad value
Note: This Device does not perform EXTEST, INTEST or the preload portion of the PRELOAD command in IEEE 1149.1.
19
HM67S36130 Series
Boundary Scan Order
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Bump ID 5R 4P 4T 6R 5T 7T 6P 7P 6N 7N 6M 6L 7L 6K 7K 5L 4L 4K 4F 5G 7H 6H 7G 6G 6F 7E 6E 7D 6D 6A 6C 5C 5A 6B 5B Signal Name M2 SA3 SA4 SA5 SA6 ZZ DQa0 DQa1 DQa2 DQa3 DQa4 DQa5 DQa6 DQa7 DQa8 SWEa K K G SWEb DQb0 DQb1 DQb2 DQb3 DQb4 DQb5 DQb6 DQb7 DQb8 SA7 SA8 SA9 SA10 NC SA11 Bit # 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Bump ID 3B 2B 3A 3C 2C 2A 2D 1D 2E 1E 2F 2G 1G 2H 1H 3G 4D 4E 4G 4H 4M 3L 1K 2K 1L 2L 2M 1N 2N 1P 2P 3T 2R 4N 3R Signal Name SA12 NC SA13 SA14 SA15 SA16 DQc0 DQc1 DQc2 DQc3 DQc4 DQc5 DQc6 DQc7 DQc8 SWEc NC SS NC NC SWE SWEd DQd0 DQd1 DQd2 DQd3 DQd4 DQd5 DQd6 DQd7 DQd8 SA0 SA1 SA2 M1
20
HM67S36130 Series
Notes: 1. Bit#1 is the first scan bit to exit the chip. 2. NC pads listed in the TABLE are represented in the Boundary Scan Register by a Place Holder. Place Holder registers are internally connected to VSS. 3. The clock pins (K and K) are needed as PECL differential levels. And, clock reciever generated single clock signal. This signal and its inverted signal are used for Boundary Scan Register input signal.
ID register
Bit# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4M, 16M Depth 4M, 16M Width
Value X X X X 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Vendor Revision No. Depth Width Use in the future Vendor ID No. Fix
21
HM67S36130 Series
TAP Controller State Diagram
Test-LogicReset 0 Run-Test/ Idle 1 SelectDR-Scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 1 0 1 SelectIR-Scan 0 1 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 1 0 1
1
0
Note:
The value adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. No matter what the original state of the controller, it will enter Test-Logic-Reset when TMS is held high for at least five rising edges of TCK.
22
HM67S36130 Series
Package Outline
HM67S36130BP (BP-119) Unit : mm
0.20
4x
A 0.35 C -A-C6 x 1.27
4-C1.2
14.00
Pin 1 Index 21.0 0.10
-B13.0 0.10
0.60 0.10
2.10
HITACI CODE JEDEC CODE EIAJ CODE Weight
0.15 C
22.00
BP-119 MO-163
119- 0.75 0.15 0.30 S C A S B S 0.10 S
1.0g
Details of the part A
16 x 1.27
23
HM67S36130 Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
24
HM67S36130 Series
Revision Record
Rev. 0 1 Date Oct. 1, 1996 Feb. 21, 1997 Contents of Modification Initial issue P1. 3.3V 0.1V Operatiion to 3.3V 5% Operation Change HM67S18258BP-7H to HM67S18258BP-7 VDDmin 3.2 to 3.135 VDDmax 3.4 to 3.465 VDDQmin 3.2/.6 to 3.135/2.375 VDDQmax 3.4/2.6 to 3.465/2.75 I DDmax 500 to 600 I OH 2mA to -2mA I OL -2mA to 2mA P.7 Change termination load t KHKL 3.2 to 2.0 t KLKH 3.2 to 2.0 Add tKHQZmin Add Note 2 Delete Soft Error Rate Drawn by -- (Y.Matsui) Approved by K.Mitsumoto S.Nakazato
25

▲Up To Search▲

Price & Availability of HM67S36130SERIES

	To Download HM67S36130SERIES Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .